1. Field of the Invention
The present invention relates generally to the field of semiconductor fabrication and, more particularly, to a process of fabricating transistors having sidewall spacers.
2. Description of Related Art
The use of sidewall spacers in the formation of metal-oxide-semiconductor (MOS) transistors is well known. A spacer is a structure located adjacent to the sidewalls of a transistor's gate. After forming the transistor gates, the spacers are typically formed by following a conformal deposition process with an anisotropic etch. Portions of the deposited film adjacent vertically oriented portions of the pre-deposition topography remain after the etch. Sidewall spacers provide an implant block that enables, for example, lateral displacement of heavily doped source/drain regions from the edges of the transistor gate. This displacement is beneficial in reducing short channel effects of submicrons and deep submicron transistors. In addition, spacers tend to lessen the severity of the wafer topography thereby facilitating subsequent fabrication processes.
In conventional transistor design, the spacers are ideally intended to be electrically inactive. Other than the electrical effects caused by the lateral displacement of the source/drain regions relative to the transistor gate, the spacer is not supposed to effect the operating characteristics of the transistor. Unfortunately, some of the more prevalent spacer materials tend to impact the transistor's performance. Specifically, dielectric materials including silicon nitride are well known to impart stress on the films over which they are deposited. This stress can affect parameters including electron mobility, defect generation, and dopant activation in the underlying substrate thereby altering the transistor's performance. Even worse, these stress effects tend to be non-symmetrical with respect to n-channel and p-channel transistors in a CMOS process.